Transient suppression for boost regulator

ABSTRACT

A circuit for generating an output voltage to a top node of a plurality of LED strings. The circuit includes an inductor having a load current flowing therethrough and a switching transistor responsive to a switching control signal. An integrator generates a compensation voltage responsive to a voltage at a bottom node of the LED string and a reference voltage. Circuitry for combining an a correction offset with the compensation voltage is responsive to the compensation voltage and the load current through the inductor. The offset is generated only during a step load change of the load current and substantially reduces voltage transients from the compensation voltage and the output voltage. A summation circuit sums the compensation voltage including the correction offset with at least the voltage at the bottom node of the LED string to generate a first control signal. A latch generates the switching control signal responsive to the first control signal and a leading edge blanking signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a reissue of U.S. application Ser. No. 12/492,755,filed Jun. 26, 2009, which claims the benefit of priority from U.S.Provisional Application Ser. No. 61/080,947, filed Jul. 15, 2008, andentitled MUTLI-CHANNEL MULTI-CHANNEL LED DRIVER, the specification ofwhich is incorporated herein by reference in its entirety.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding, reference is now made to thefollowing description taken in conjunction with the accompanyingDrawings in which:

FIG. 1 is a block diagram of an LED driver circuit;

FIG. 2 illustrates is a simplified block diagram more fully illustratingcircuitry for implementing dynamic headroom control within an LED drivercircuit;

FIG. 3 is a flow diagram describing the operation of the circuit of FIG.2;

FIG. 4 is a simplified block diagram more fully describing the mannerfor transient suppression within the boost converter of the LED driver;

FIG. 5 illustrates the boost transients created by changes in the loadat the output of the LED driver;

FIG. 6 illustrates the manner in which the circuitry of FIG. 4suppresses the boost transients responsive to a change in the inductorload current;

FIG. 7 is a flow diagram describing the operation of the circuitry forsuppressing the boost transients;

FIG. 8 is a simplified block diagram illustrating the manner forproviding boost ripple rejection within the LED driver; and

FIGS. 9a and 9b disclose wave forms illustrating operation of thecircuit of FIG. 8 both with and without the use of sample and holdcircuitry.

DETAILED DESCRIPTION

Referring now to the drawings, wherein like reference numbers are usedherein to designate like elements throughout, the various views andembodiments of DYNAMIC HEADROOM CONTROL FOR LED DRIVER are illustratedand described, and other possible embodiments are described. The figuresare not necessarily drawn to scale, and in some instances the drawingshave been exaggerated and/or simplified in places for illustrativepurposes only. One of ordinary skill in the art will appreciate the manypossible applications and variations based on the following examples ofpossible embodiments.

LED drivers are used for driving LEDs in various applications. Multichannel LED drivers may be used for driving multiple strings (i.e.,channels) of LEDs for use in various applications such as backlighting.Existing LED drivers may have problems providing sufficient headroom forthe LED strings and may also experience excessive transients within theoutput of switching converters within the LED driver due to changes inload currents.

Referring now to the drawings, and more particularly to FIG. 1, there isillustrated a block diagram of one embodiment of an LED driver 102. TheLED driver 102 is connected to drive multiple LED strings 104. Thedriver 102 of FIG. 1 controls eight channels of LED current to enablethe LED strings 104 to be used for LCD backlight applications. The drivevoltage for the LED strings is regulated from an input voltage node 106by switching the current in an inductor 108. The drive voltage isprovided to the top of each LED string 104. Voltages at the bottom ofeach LED string 104 are monitored by Dynamic Headroom Control block 110to determine the voltage at the bottom of each string. Amplifier 112generates a COMP voltage at node 114 responsive to voltage informationfrom the feedback stack connected to the pot-down from the drive voltagefed into the OVP block. The COMP voltage from node 114 along with otherinformation are input to a summation circuit 116 that provides a controloutput to control logic 118 for controlling the FET driver circuitry 120controlling the operation of a switching transistor 122 which in turnregulates LED drive voltage by controlling the current in the inductor108.

Referring now to FIG. 2, there is illustrated a simplified block diagramof the circuitry used for providing dynamic headroom control within theLED driver 102. Within the LED driver 102, multiple channels of LEDstrings 204 are operated using a boost controller 202 and a boostconverter (including components 202, 207, 208, 212, 216, 218, and 220)to generate a voltage that is applied to the top of several stacks ofseries LED strings 204 which are each connected in parallel to aseparate current source at the bottom end of the LED string 204. Whilethe illustration in FIG. 2 only presents a single LED string 204connected with the boost converter, in operation multiple LED strings204 are connected with the boost converter such that multiple iterationsof the circuit block 206 would exist, one for each LED string. The inputvoltage V_(IN) is applied to a first side of an inductor 207. The otherside of the inductor 207 is connected to an anode of diode 208 at node210. A capacitor 212 is connected between the cathode of diode 208 andground. The cathode of diode 208 is connected to the top of the LEDstring 204 at node 214. A switching transistor 216 has its drain/sourcepath connected between node 210 and node 218. The gate of transistor 216receives drive signals from the boost controller 202. Node 218 isconnected to the current sense (CS) input of the boost controller 202. Aresistor 220 is connected between node 218 and ground.

The top of the LED string at node 214 comprises an output voltage nodeV_(OUT) which is connected to a resistor divider consisting of resistors222 and 224. Resistor 222 is connected between node 214 and node 226.Resistor 224 is connected between node 226 and ground. A voltagemeasurement is taken at node 226 (from the pin usually used for overvoltage protection purposes) and provided to the boost regulator 202 asa feedback voltage V_(FB). The LED string 204 consists of a plurality ofindividual LEDs 215 which are connected in series between node 214 andnode 228. A current source is provided at the bottom of the LED stringat node 228. The current source consists of an amplifier 230 connectedto receive a reference voltage VSET at the non-inverting input. Thevoltage VSET is used to set the current. The output of the amplifier 230is connected to a transistor 232 having its drain/source path connectedbetween node 228 and node 234. The other input of amplifier 230 isconnected to node 234. The inverting input of amplifier 230 is connectedto node 234. A resistor 236 is connected between node 234 and ground.The disclosed embodiment comprises one example of the current source.However, other implementations of the current source may be used.

The voltage generated at node 228 is applied to the non-inverting inputof comparators 238 and inverting input of comparator 240. The invertinginput of comparator 238 is connected to receive a reference voltageV_(HIGH). The non-inverting input of comparator 240 is connected toreceive a reference voltage V_(LOW). The output of comparator 238 isconnected to one input of an AND gate 242. The remaining inputs of ANDgate 242 would be connected to the outputs of the comparator 238 fromeach of the other channels associated with each of the other circuitblocks 206. Similarly, the output of comparator 240 is connected to oneinput of an OR gate 244. The remaining inputs of OR gate 244 would beconnected to the outputs of the comparators in each of the otherchannels from circuit block 206. The output of AND gate 242 is providedto the DOWN input of counter/stepping algorithm 246. The output of ORgate 244 is connected to the UP input of the counter/stepping algorithm246. The counting/stepping algorithm 246 generates a count value via bus248 that is input to a digital-to-analog converter 250. Thedigital-to-analog converter 250 generates an output analog value that isused as the reference voltage V_(REF) that is applied back to the boostregulator circuitry 202.

The multi-channel LED configuration using a boost/buck switchingregulator generates a single voltage at node 214 to drive the top of aplurality of series LED strings 204. Each of the series stacks of LEDstrings 204 are connected in parallel to a separate current source atthe bottom node 228. This allows a savings in circuit hardware bysharing the switching regulator between multiple LED strings 204. Thisconfiguration drives a large number of LEDs without requiringexcessively high voltages. However, the voltages must be carefullyregulated to eliminate power dissipation in the current sources whichwill cause thermal problems and limit overall circuit efficiency. As thevoltage of the LEDs are variable (with process, temperature and agingeffects), previous implementations of these systems have used thevoltage at the output of the current sources at node 228 as a feedbackpoint for the regulator allowing the regulator to be adaptive and movethe optimum operating level. This minimizes power dissipation due to thevoltage drop across the current source. Typically this is done bypassing the analog voltages at the bottom of each LED string 204 to acontrol block which picks out the lowest voltage level from each of theLED strings and passes this selected voltage on as the feedback voltage.This feedback voltage is regulated to a level which has been definedsuch that the current sources will have sufficient headroom not to bepushed in a linear region of operation (typically several hundredmillivolts). This works well when all LED strings are running with thesame pulse width modulated (PWM) dimming signal, as whenever any stringis conducting, all strings are conducting. This means that real timeinformation is available on which string has the lowest voltage at alltimes when the boost voltage regulator is switching.

However, for systems where different PWM dimming signals are used fordifferent channels, it is possible for there to be no time when allchannels are conducting at once. It would be possible to regulate on thebasis of only those channels that are conducting at a given point intime, resulting in a switching regulator output voltage level whichvaries as different channels turn on and off. However, this solutionprovides a poor output voltage transient response resulting in shortcurrent pulses being noticeably compressed in situations where there isa mismatch between strings.

If, for example, all LED strings 204 have the same conducting voltage,except for one which needs one volt more, and the LED string is onlyturned on for a 490 nanosecond pulse every 500 microseconds (as would bethe case with the lowest dimming signal in a 10-bit PWM dimming schemerunning on a 2 KHz PWM frequency), the boost regulator 202 would have torespond in substantially less than this time. It is not practical tobuild the boost regulator 202 for such an application that has atransient response that is dynamically faster than 490 nanoseconds. Inpractice, the response time will be a period of tens to hundreds ofmicroseconds, which is far too slow. This means that the boost regulator202 will miss the 490 nanosecond period when the circuit requires extrahead room, which in turn is likely to mean that the current source hasinsufficient headroom and that the 490 nanosecond current pulse will notreach its intended peak current. This compression of current will causea corresponding reduction of the brightness of the LED string, for thelower PWM duty cycles and strings with higher forward voltages thanother strings in the system. The implementation described with respectto FIG. 2 uses a different approach to determine the switching regulatoroutput voltage provided by the boost voltage regulator 202.

The voltage window between the reference voltages V_(HIGH) and V_(LOW)is set to be larger than the smallest single step that can be introducedonto the boost regulator output voltage node 214 by the control scheme,guaranteeing that at least one output level will obtain a stableoperating point. The voltage control is achieved by regulating theoutput voltage of the boost regulator 202 to a reference voltage inputV_(REF) that is generated from the digital-to-analog converter (DAC)250. The counter/stepping algorithm 246 controls the reference voltageprovided by the DAC 250 to cause the voltage at the bottom of a lowestvoltage node of the plurality of LED strings 204 to remain between thehigh reference voltage and the low reference voltage The DAC 250 outputcan be moved up and down to the required level by digital controlsignals provided from the counter/stepping algorithm 246 to the requiredlevel by a digital control scheme based upon information gained frommonitoring the channel voltages at the bottom of each LED string 204.The OVP signal monitored at node 226 is used as the feedback signal forthe boost regulator 202, which is regulated to the voltage leveldictated by the reference voltage provided from the DAC 250. Thisprovides the correct voltage for the LED string 204 with the highestforward voltage requirement no matter how short the time a particularLED string is conducting. Additionally, stability is improved oversystems which take the boost feedback from the bottom of the LEDstrings, as the phase shift that would normally be introduced into thefeedback path due to the interaction with the current source transientresponse and LED characteristics is eliminated from the control loop.

The DAC 250 is configured such that successive changes get larger andlarger (up to a maximum step size limit) in order to reach a targetpoint, unless the output remains constant for longer than a certain timeor changes direction. Any subsequent changes will be small to allow forminor fluctuations in the level required for temperature variations inthe forward voltage of the LEDs, and those caused by noise in thesystem. The control algorithm is optimized to enable the output voltageto fall faster than it can rise as if the output voltage is too high, itcan quickly cause thermal problems for the LED driver.

The LED driver monitors the switching regulator output voltage at node226 to prevent the reference voltage V_(REF) from being changed if theboost regulator has not caught up with the target reference value andgenerates an output voltage responsive to the reference voltage. Thisprevents the reference voltage from “running away” from the requiredvalue and taking a long time to come back in line once the boostregulator 202 has caught up. This is particularly important when theboost regulator 202 output voltage is dropping. This is due to the factthat the boost regulator 202 can produce a very fast rise in the outputvoltage, but the only way to reduce the output voltage is to allow thecurrent source to discharge the output capacitor during its normalconduction time. This can take a significant amount of time to lower theoutput voltage if the LED duty cycles are very low. Thus, the systemwill not allow the reference voltage to be changed upwards if thefeedback of the output level is significantly below the currentreference voltage and will not allow the reference voltage to be changeddownwards if the feedback of the output level is significantly above thecurrent reference voltage. The configuration also provides over voltageprotection without requiring additional circuitry as there is a maximumDAC code above which the boost regulator 202 will not go. This level canbe modified by changing the pot down ratio to the pin.

Referring now to FIG. 3, there is illustrated a flow diagram describingthe operation of the circuit of FIG. 2. Voltage information is measuredat step 302 at the bottom of each LED string 204 at node 228. Thisinformation is not fed to the boost regulator 202 in real time asfeedback to the FB pin. Instead, the output voltage at node 214 ismonitored through the voltage divider circuit consisting of resistors222 and 224. The feedback voltage to the FB pin is provided from node226 of the resistor divider. A voltage window is created between thereference voltages V_(HIGH) and V_(LOW) using comparators 238 and 240.Using these two comparators 238 and 240, the circuit attempts toregulate the lowest channel voltage on an LED string during conductionof the LED string. If inquiry step 312 determines if at least one of thevoltages at node 228 is below a reference voltage V_(LOW) duringconduction, this causes the associated comparator 240 on that channel togo to a logical “high” level which drives the output of OR gate 244 to alogical “high” level generating an UP signal at step 314. The logical“high” signal at the output of OR gate 244 causes the counter/steppingalgorithm 246 and DAC 250 to increase the reference voltage V_(REF) atstep 316. The increased reference voltage V_(REF) causes a correspondingincrease at step 318 of the regulated voltage provided by the boostregulator 202.

If inquiry step 312 determines that none of the voltages at node 228 ofthe LED strings fall below the referenced voltage V_(LOW), inquiry step304 determines whether during the entire PWM period all channelsassociated with each LED string 204, except those channels which arecompletely turned off (i.e., 0% PWMs/disabled), were conducting at leastonce and whether all channels had a voltage at the bottom of its LEDstring that was above V_(HIGH) during conduction. If so, the regulatedvoltage is reduced by the counter/stepping algorithm 246. In thiscircumstance, the output of the comparator 238 would be at a logical“high” level for each LED string being driven by the LED driver, andthese signals would drive the output of the AND gate 242 to a logical“high” level generating the DOWN signal at step 306. Responsive to theDOWN signal, the reference voltage V_(REF) is decreased by thecounter/stepping algorithm 246 and DAC 250 at step 308. The reducedreference voltage provided by the DAC 250 will cause a correspondingdecrease in the regulated voltage provided at node 214 by the boostregulator 202 at step 310.

If inquiry step 304 determines that all channel voltages at node 228 arenot above the reference voltage V_(HIGH) for the entire PWM period, atleast one of the voltages at nodes 228 is within the established voltagewindow, and the reference voltage is maintained at step 320. This causesthe regulated voltage to be maintained at the established level at step322. The process continues at step 324 and returns back to step 302 tocontinue monitoring the voltage at the bottom of each LED string at node228.

Referring now to FIG. 4, there is more particularly illustrated analternative embodiment the circuitry within the boost regulator 202 forproviding transient suppression within the output voltage V_(OUT)provided from node 210. The boost regulator 202 transients at knownsteps can be dramatically reduced by adding an offset to the COMPvoltage V_(COMP) at the same time the load current IL through inductor207 changes. The COMP voltage V_(COMP) is provided from the output of anintegrator 402. Addition of the offset to the output of the integrator402 saves the integrator 402 from having to settle to a new value, andthe resulting over/under current delivered to the output during thesettling time. This configuration however does not change the basic loopproperties in each load condition. The integrator 402 receives thefeedback voltage FB from node 228, at the bottom of LED stack 204,although it can also be configured as in FIG. 2. Additionally, theintegrator 402 receives at a second input a reference voltage V_(REF)404. The output of the integrator 402 is connected to an adder circuit406 and a control algorithm and DAC 408 through node 410. Also connectedto node 410 is a capacitor 412 connected between node 410 and ground.

The control algorithm and DAC 408 generates a correction offset that isadded with the COMP voltage provided from the output of the integrator402 to dramatically reduce the boost transients as described hereinabove. The control algorithm and DAC 408 generates the correction offsetresponsive to the provided COMP voltage and provided load informationprovided from control input 414. The load information would comprise theload current through inductor 207. The COMP voltage including thecorrection offset is provided to the inputs of a summation circuit 416.Also provided as input to the summation circuit 416 are a slopecompensation ramp signal, the feedback voltage V_(FB), the referencevoltage V_(REF), the voltage monitored at node 218 at the source ofswitching transistor 216 and connections to system ground. The output ofthe summation circuit 416 is provided as a control output to the R inputof a latch circuit 418. The latch circuit 418 also receives at its Sinput, a leading edge blanking signal (LEB). The leading edge blankingsignal is a fixed frequency clock signal with a very low duty cycle(short “HIGH” time) which set the 418 flip flop. It can be used as aleading edge blanking signal, as well, if the flip flop 418 is setdominant. The flip-flop 418 generates at its Q output drive signals tothe switching transistor 216.

In a switching regulator 202, when a proportional control scheme isused, load regulation is very poor. Any increase in the load currentthrough inductor 207 that is above the conduction point of the inductor207 will result in a corresponding decrease in the output voltageV_(OUT). However, while the response to a load step causes a change inthe output voltage level, the time taken to settle to the new voltagelevel is very fast. In an integral system, extra gain at low frequenciesis used to eliminate most of this load regulation characteristic. Thisis at the expense of a fast transient response, as the system can onlyrespond to a transient with a bandwidth defined by the integrator gm andloop filter (COMP) network impedance. This means that a step increase inthe load current will cause an initial output voltage fall followed by acorrection. Likewise, when a load is reduced in a step, the initialtransient is in a positive direction. The larger the load currenttransient, the larger the corresponding output transient. Thesescenarios are more fully illustrated in FIG. 5.

Referring now to FIG. 5, there are illustrated the changes in the loadcurrent 502, the compensation voltage 504 and the output voltage 506over a period of time. As can be seen, when there is a step increase inthe load current 502 at times T₁, T₂ and T₄, a corresponding transientincrease in the COMP voltage 504 occurs before the COMP voltage settlesto a steady state level. Responsive to the COMP voltage 504, the outputvoltage V_(OUT) goes through a transient spike decrease, until theoutput voltage settles back to the regulated voltage level. Also, whenthere is a step decrease in the load current 502, the COMP voltagereacts with a corresponding decrease, and the regulated output voltageV_(OUT) 506 incurs a transient spike increase prior to settling back tothe regulated voltage levels. These load transients can be dramaticallyreduced by adding the offset from the control algorithm and DAC 408 tothe COMP voltage at adder 406 at the same time as the load changes asindicated by the load information provided at input 414. This saves theintegrator 402 from having to settle to a new feedback voltage level andthe resulting over/under current delivery to the output during thesettling time. The configuration has the added benefit of not changingthe basic loop properties in each load condition.

There is a component in these transients illustrated in FIG. 5 that iscaused by the time taken to ramp the inductor current I_(L) UP or downto a new value that is difficult to correct for. However, this is notthe dominant term. The implementation illustrated in FIG. 4 applies tosystems where the load is known, and it is possible to correct for theremainder of the change. This is particularly relevant to a circuitincluding multi-string LED drivers where there are a known set ofdiscrete possible loads. Any load regulation or transient spikecharacteristics in such systems have the potential to cause increasedpower dissipation in the LED driver and also may push the currentsources into their linear regions of operations. The latter conditionrequires that a system must either be designed to give enough headroomin the current sources, such that these events do not push them intotheir linear region of operation, thus increasing on-chip powerdissipation or, alternatively, accepting poor LED current control thatwill result from many transitions into the linear region.

For example, if the circuit is designed to drive 8 stacks of LEDs, thereexists 9 possible load conditions. These load conditions are 0 amps (allstacks off), I_(LED) (one stack conducting), 233 I_(LED) (two stacksconducting), . . . 8×I_(LED) (all 8 stacks conducting). Thus, over thecourse of operation, a control term specific to each of these loadconditions may be provided. The control scheme related to the circuit ofFIG. 4 attempts to provide an input to the loop that reduces the amountof voltage shift required to the integrator output node. This allows theintegral control to be kept in the loop while eliminating the maincomponent to the transient voltage event.

This may be accomplished by the control algorithm and DAC 408 in anumber of ways. In a first embodiment, a simple scheme uses a gain termthat amplifies the input to the loop defined by the integrator 402.Given that the integral term is proportional to the inductor currentI_(L) (beyond the continuous conduction point), the gain may be variedto attempt to reduce the total range of the integrator 402 output overthe range of possible load currents. In an LED driver system which usesPWM controls to dim the LEDs, a differential gain can be applied to eachpossible load combination (0 to N LED strings conducting), providing amuch reduced integrator output swing, and therefore smaller voltagetransients. This can be based on calculations of the inductor current atthe time of design or simulation based, where a gain is picked viasimulations that show the characteristics of the integrator outputduring the various load conditions. In non LED systems where the load isknown but has many more states than is practical to implementdiscretely, the gain term can be continuous with a relationship betweenload and gain developed to best fit the application. This probably willnot give a perfect fit, but so long as the total integrator range isreduced, the transient response is improved.

In an alternative embodiment, a more complex scheme can be used withdiscrete load steps. The integrator output can be monitored and make useof a digital control scheme to attempt to pull the output value to aknown level. For example, the integrator output voltage goes up inresponse to a higher load current, and the system will add acontribution to the loop via the digital-to-analog controller (DAC)within block 408 to try and bring down the output voltage. Similarly, acontribution is removed from the loop when the output voltage goes downin order to attempt to bring it back up to a desired level. The latestdigital-to-analog controller code used can be stored for each possibleload level and applied at the start of any condition where theparticular load is presented. In this manner, the system can build upand use a stored predetermined set of offset values as inputs to theloop to limit the range of the integrator output and minimize outputvoltage transients. The advantage of this method over the firstalternative is that the effective gain of the integrator term in theloop does not change with load level and proportional control can stillbe carried out by use of a resistor in series with the compensationcapacitor without providing varying proportional gains of the loadcurrent.

Referring now to FIG. 6, there is illustrated a flow diagram describingthe operation of the boost regulator 202 utilizing the described controlalgorithm. Initially, at step 602 a determination is made of thecompensation voltage responsive to the FB voltage and the V_(REF)voltage by the integrator 402. The control algorithm within block 408determines a control offset value responsive to the providedcompensation voltage and the load information as indicated by the numberof LED strings 204 conducting. The generated offset control valuecontrols the digital-to-analog converter within the control block 408 togenerate the correction offset analog voltage which is added at step 606to the compensation voltage within the adder circuit 406. The offsetcompensation voltage is used in generating the output voltage throughthe summation circuit 416 and latch 418 that generate the switchingcontrol signals controlling at step 608 the output voltage V_(OUT) atnode 210.

Referring now to FIG. 7, there is illustrated the load current I_(L)702, the COMP voltage 704 and the output voltage V_(OUT) 706 for asystem using the boost transient suppression method described hereinabove. As described previously, the load current increases at times T₁,T₂ and T₄. Unlike in the wave forms illustrated with respect to FIG. 5,the COMP voltage 704 settles very quickly as the levels are very closeto the previous levels due to the added COMP voltage offset.Consequently, within the output voltage signal V_(OUT) 706 only smalltransient voltage spikes remain which are caused by the time taken toramp the inductor current to the new level. A similar situation can beseen in cases where the load current is stepped down at times T₃ and T₅.Comparisons between the illustrations in FIGS. 5 and 7 illustrate thesignificant transient suppression provided by the use of the correctionoffset with the voltage compensation signal.

Referring now to FIG. 8, there is illustrated the manner in which theboost regulator 202 may be configured to provide ripple rejection.Integral control is included within the DC/DC controller loops via theintegrator 402 as described previously to improve absolute accuracywhile maintaining a smaller output capacitor than would be required bythe same accuracy in equivalent proportional control schemes. Thevoltage ripple on the DC/DC output is defined by a number of factorsincluding V_(IN), V_(OUT), I_(LOW), I inductor value, output capacitanceand output capacitance capacitor effective series resistance. These arerelated via the following equations:Duty cycle D=(V_(out)−V_(in))/V_(out)Avg inductor current ILavg (average)=Iload*Vout/(Vin*efficiency)Peak inductor current ILpeak=ILavg+V_(in)/L*D*T*0.5 (for continuoussystem)Capacitor ripple current Iripple=ILpeakCapacitor ripple voltage Vripple=ESR*ILpeak

In a given system, where most of these terms are defined, the importantfigures for defining ripple are the peak inductor current which isdefined by the load current and other factors, and the output capacitorESR. In high voltage applications such as an LED driver where many LEDsare connected in series, the type of capacitors used to obtain therequired output capacitances can have a relatively high ESR. This canprovide high level output ripple. The operation of the integral controlscheme will mean that the average value of this ripple wave form will beregulated to the required level. For most applications this isacceptable. However, LED driver systems attempt to regulate the voltageat the top of an LED string such that the voltage at the bottom is onlyjust enough for the current source to function properly. This is done tominimize power dissipation in the LED driver. If this lower level isregulated to the average of the target level, the lower portions of theripple are below the target and they push the current source into itslinear region of operation. This will get worse as the load current andESR increase and also if the number of LEDs increases thus increasingthe inductor current. To solve this, the target voltage must be raisedto guarantee that it does not affect operation. This is difficult to doin practice and will result in the headroom for the current sourcesbeing set higher than required to guarantee that there is never aproblem, increasing potential power dissipation in cases where it is notneeded.

FIG. 8 illustrates a boost converter providing a new method for applyingthe feedback signal at the FB pin to the input of the integrator 402.The input of the FB pin which is normally fed to both the integrator 402and the voltage feedback term in the control loop of the summationcircuit 416 in the control loop is sampled and held by a switch 802 onthe input to the integrator 402. By sampling and holding this voltagewhen the switching node is at a logical “low” level at the output queueof flip-flop 418, the integrator 402 sets the regulation point to thelowest point in the output ripple wave form. This allows the portions inthe wave form to align with the reference voltage. This means that theheadroom of the current source can be set to a much lower level whileguaranteeing that ripple will not be able to push the current sourcesinto their linear regions of operation.

Referring now to FIGS. 9a and 9b, there are illustrated the inductorcurrent I_(L) and reference voltage feedback (FB) waveforms with respectto a circuit not using the sample and hold switch (FIG. 9a) and acircuit using the sample and hold switch (FIG. 9b). When the sample andhold circuit is not used, the feedback voltage falls below the referencevoltage V_(REF) at a number of points during operation. FIG. 9billustrates the use of a sample and hold circuit and the feedbackvoltage FB remains above the reference voltage V_(REF) at all timesindependent of the provided load current I_(L).

The boost regulator produces the minimal voltage needed to enable theLED string 204 with the highest forward voltage drop to run at theprogrammed current. The circuit employs a current mode control boostarchitecture that has a fast current sense loop and a slow voltagefeedback loop. This architecture achieves a fast transient response thatis essential for notebook backlit applications where the power can be aserious drain on batteries or instantly charged to an AC/DC adaptorwithout rendering noticeable visual nuisance. The number of LEDs thatcan be driven by the circuit depends on the type of LED chosen by theapplication.

The circuit is capable of boosting up to 34.5 volts and driving 9 LEDsin series for each channel. However, other voltage boost levels andnumbers of LEDs may be supported in alternative embodiments. The dynamicheadroom control circuit controls the highest forward voltage LED stackor effectively the lowest voltage from any of the input current pins.The input current pin at the lowest voltage is used as a feedback signalfor the boost regulator. The boost regulator drives the output to thecorrect levels such that the input current pin at the lowest voltage isat the target headroom voltage. Since all of these LED strings areconnected to the same output voltage, the other input current pins willhave a higher voltage, but the regulated current source on each channelwill ensure that each channel has the same programmed current. Theoutput voltage will regulate cycle by cycle and is always referenced tothe highest forward voltage string in the architecture.

It will be appreciated by those skilled in the art having the benefit ofthis disclosure that this LED driver provides an improved operatingcharacteristic when driving LED strings in multiple channels. It shouldbe understood that the drawings and detailed description herein are tobe regarded in an illustrative rather than a restrictive manner, and arenot intended to be limiting to the particular forms and examplesdisclosed. On the contrary, included are any further modifications,changes, rearrangements, substitutions, alternatives, design choices,and embodiments apparent to those of ordinary skill in the art, withoutdeparting from the spirit and scope hereof, as defined by the followingclaims. Thus, it is intended that the following claims be interpreted toembrace all such further modifications, changes, rearrangements,substitutions, alternatives, design choices, and embodiments.

What is claimed is:
 1. A circuit for generating an output voltage to atop node of a plurality of LED strings, comprising: an inductor having aload current flowing therethrough; a switching transistor responsive toa switching control signal; an integrator for generating a compensationvoltage responsive to a voltage at a bottom node of an LED string and areference voltage; circuitry for combining an offset with thecompensation voltage responsive to the compensation voltage and the loadcurrent through the inductor, wherein the offset is created only duringa step load change of the load current and substantially reduces voltagetransients from the compensation voltage and the output voltage; asummation circuit for summing the compensation voltage including theoffset with at least the voltage at the bottom node of the LED string togenerate a first control signal; a latch for generating the switchingcontrol signal responsive to the first control signal and a leading edgeblanking signal.
 2. The circuit of claim 1, wherein the circuitry forcombining further comprises: control logic for generating the offsetresponsive to the compensation voltage and the step load change of theload current; and an adder circuit for adding the offset to thecompensation voltage to substantially reduce the voltage transients. 3.The circuit of claim 2, wherein the control logic further comprises:circuitry for implementing a control algorithm for generating a digitalvalue of the offset responsive to the compensation voltage and the stepload change of the load current; and a digital to analog converter forgenerating the offset in analog format responsive to the digital valueof the offset.
 4. The circuit of claim 1, wherein the summation circuitfurther sums the compensation value, the voltage at the bottom node ofthe LED string, a slope compensation ramp signal and a current sensesignal to generate the first control signal.
 5. The circuit of claim 1,wherein basic loop properties of the circuit remain unchanged in eachload condition.
 6. The circuit of claim 1 further including a sample andhold circuit between the integrator and the bottom node of the LEDstring.
 7. A circuit for generating an output voltage to a top node of aplurality of LED strings, comprising: an inductor having a load currentflowing therethrough; a switching transistor responsive to a switchingcontrol signal; an integrator for generating a compensation voltageresponsive to a voltage at a bottom node of the an LED string and areference voltage; circuitry for implementing a control algorithm forgenerating a digital value of an offset responsive to the compensationvoltage and a step load change of the load current; a digital to analogconverter for generating the offset in analog format responsive to thedigital value of the offset; an adder circuit for adding the offset tothe compensation voltage to substantial reduce the voltage transientsfrom the compensation voltage and the output voltage; a summationcircuit for summing the compensation voltage including the offset withat least the voltage at the bottom node of the LED string to generate afirst control signal; and a latch for generating the switching controlsignal responsive to the first control signal and a leading edgeblanking signal.
 8. The circuit of claim 7, wherein the summationcircuit further sums the compensation value, the voltage at the bottomnode of the LED string, a slope compensation ramp signal and a currentsense signal to generate the first control signal.
 9. The circuit ofclaim 7, wherein the basic loop properties of the boost regulator remainunchanged in each load condition.
 10. The circuit of claim 7 furtherincluding a sample and hold circuit between the integrator and thebottom node of the LED string.
 11. A method for generating an outputvoltage to a top node of a plurality of LED strings, comprising thesteps of: generating a compensation voltage responsive to a voltage at abottom node of an LED string and a reference voltage; generating anoffset voltage only during a step load change of the load current;combining the offset voltage with the compensation voltage, wherein theoffset voltage substantially reduces voltage transients from thecompensation voltage and the output voltage; summing the compensationvoltage including the offset voltage with at least the voltage at thebottom node of the LED string to generate a first control signal;generating a switching control signal responsive to the first controlsignal and a leading edge blanking signal; and generating the outputvoltage responsive to an input voltage and the switching control signal.12. The method of claim 11, wherein the step of combining furthercomprises the step of adding the offset voltage to the compensationvoltage to substantially reduce the voltage transients.
 13. The methodof claim 11, wherein the step of generating an offset voltage furthercomprises the steps of: generating a digital value of the offset voltageresponsive to the compensation voltage and the step load change of theload current with a control algorithm; and converting the digital valueof the offset voltage into the offset in an analog format.
 14. Themethod of claim 11, wherein the step of summing further comprises thestep of summing the compensation value, the voltage at the bottom nodeof the LED string, a slope compensation ramp signal and a current sensesignal to generate the first control signal.
 15. The method of claim 11further including the step of maintaining the basic loop properties of aboost regulator unchanged in each load condition.
 16. The method ofclaim 11 further including the step of sampling and holding the voltageat the bottom node of the LED string used to generate the compensationvoltage.
 17. A method for generating an output voltage to a top node ofa plurality of LED strings, comprising the steps of: generating acompensation voltage responsive to a voltage at a bottom node of an LEDstring and a reference voltage; generating an offset voltage only duringa step load change of the load current; combining the offset voltagewith the compensation voltage, wherein the offset voltage substantiallyreduces voltage transients from the compensation voltage and the outputvoltage; summing the compensation voltage including the offset voltagewith at least the voltage at the bottom node of the LED string togenerate a first control signal, wherein the step of summing furthercomprises the step of summing the compensation value, the voltage at thebottom node of the LED string, a slope compensation ramp signal and acurrent sense signal to generate the first control signal; generating aswitching control signal responsive to the first control signal and aleading edge blanking signal; and generating the output voltageresponsive to an input voltage and the switching control signal.
 18. Acircuit for generating an output voltage to a top node of a plurality ofLED strings, comprising: an inductor having a load current flowingtherethrough; a switching transistor responsive to a switching controlsignal; an integrator for generating a compensation voltage responsiveto a voltage at a bottom node of an LED string and a reference voltage;circuitry for combining a correction offset with the compensationvoltage responsive to the compensation voltage and the load currentthrough the inductor, wherein the offset is created only during a stepload change of the load current and substantially reduces voltagetransients from the compensation voltage and the output voltage; asummation circuit for summing the compensation voltage including thecorrection offset with at least the voltage at the bottom node of theLED string to generate a first control signal; and a latch forgenerating the switching control signal responsive to the first controlsignal and a leading edge blanking signal.
 19. The circuit of claim 18,wherein the circuitry for combining further comprises: control logic forgenerating the correction offset responsive to the compensation voltageand the step load change of the load current; and an adder circuit foradding the correction offset to the compensation voltage tosubstantially reduce voltage transients on the compensation voltage andthe output voltage.
 20. The circuit of claim 19, wherein the controllogic further comprises: circuitry for implementing a control algorithmfor generating a digital value of the correction offset responsive tothe compensation voltage and the step load change of the load current;and a digital to analog converter for generating the correction offsetin analog format responsive to the digital value of the correctionoffset.
 21. The circuit of claim 18, wherein the summation circuitfurther sums the compensation value, the voltage at the bottom node ofthe LED string, a slope compensation ramp signal and a current sensesignal to generate the first control signal.
 22. A circuit forgenerating an output voltage to a top node of a plurality of LEDstrings, comprising: an inductor having a load current flowingtherethrough; a switching transistor responsive to a switching controlsignal; an integrator for generating a compensation voltage responsiveto a voltage at a bottom node of an LED string and a reference voltage;circuitry for implementing a control algorithm for generating a digitalvalue of a correction offset responsive to the compensation voltage anda step load change of the load current; a digital to analog converterfor generating the correction offset in an analog format responsive tothe digital value of the correction offset; an adder circuit for addingthe correction offset in the analog format to the compensation voltageto substantially reduce the voltage transients from the compensationvoltage and the output voltage; a summation circuit for summing thecompensation voltage including the correction offset with at least thevoltage at the bottom node of the LED string to generate a first controlsignal; and a latch for generating the switching control signalresponsive to the first control signal and a leading edge blankingsignal.
 23. The circuit of claim 22, wherein the summation circuitfurther sums the compensation value, the voltage at the bottom node ofthe LED string, a slope compensation ramp signal and a current sensesignal to generate the first control signal.
 24. A method for generatingan output voltage to a top node of a plurality of LED strings,comprising: generating a compensation voltage responsive to a voltage ata bottom node of an LED string and a reference voltage; generating acorrection offset voltage; combining the correction offset voltage withthe compensation voltage, wherein the correction offset voltagesubstantially reduces voltage transients from the compensation voltageand the output voltage; summing the compensation voltage including thecorrection offset voltage with at least the voltage at the bottom nodeof the LED string to generate a first control signal; generating aswitching control signal responsive to the first control signal and aleading edge blanking signal; and generating the output voltageresponsive to an input voltage and the switching control signal, whereinthe generating a correction offset voltage further comprises: generatinga digital value of the correction offset voltage responsive to thecompensation voltage and a step load change of the load current with acontrol algorithm; and converting the digital value of the correctionoffset voltage into an analog format.
 25. The method of claim 24,wherein the combining further comprises adding the correction offsetvoltage to the compensation voltage to substantially reduce the voltagetransients.
 26. The method of claim 24, wherein the summing furthercomprises summing the compensation value, the voltage at the bottom nodeof the LED string, a slope compensation ramp signal and a current sensesignal to generate the first control signal.
 27. A method for generatingan output voltage to a top node of a plurality of LED strings,comprising: generating a compensation voltage responsive to a voltage ata bottom node of an LED string and a reference voltage; generating acorrection offset voltage only during a step load change of the loadcurrent; combining the correction offset voltage with the compensationvoltage, wherein the correction offset voltage substantially reducesvoltage transients from the compensation voltage and the output voltage;summing the compensation voltage including the correction offset voltagewith at least the voltage at the bottom node of the LED string togenerate a first control signal, wherein the summing further comprisessumming the compensation value, the voltage at the bottom node of theLED string, a slope compensation ramp signal and a current sense signalto generate the first control signal; generating a switching controlsignal responsive to the first control signal and a leading edgeblanking signal; and generating the output voltage responsive to aninput voltage and the switching control signal.